The technology disclosed relates to network equipment testing. In particular it relates to pseudo-random error insertion in network traffic for testing network equipment at very high speed.
Random transmission errors may occur in digital networks such that an occasional bit becomes corrupted in the network, resulting with the received value being different from the transmitted value. The average rate at which such errors occur in a network connection is called the Bit Error Rate (BER). BERs are expressed in exponential format; for example a BER of 3.4e-3 means that, on average, 3.4 bits out of each 103 are corrupted. To test the behavior of network equipment in the presence of such random errors, test equipment simulates transmission errors by inserting random (or pseudo-random) errors, at a known and controlled average rate, into a transmitted bit-stream.
It is desirable to be able to simulate a wide range of BERs, typically from 1e-10 (one error in every 1010 bits on average) to 1e-1 (one error in every ten bits on average). Further, the distribution of errors should appear to be random. That is, when simulating a BER of (say) 1e-1, it is not acceptable for every tenth bit to be corrupted. Rather, the corruptions should appear random but with a medium term average rate tending towards one in ten.
At low network speeds, up to a few hundred Mbit/sec, the transmissions errors can be simulated with a simple pseudo-random number generator, iterating for each bit, and on each iteration comparing the pseudo-random value with a threshold value corresponding to that desired BER. However, at very high network speeds, beyond about one Gbit/sec, this is infeasible due to limitation of available logic speed in network test equipment.
In network test equipment for very high speeds the test traffic is generated many bits at a time, in parallel, typically 16, 32, 64, 128 bits at a time, corresponding to a bus width of 16, 32, 64, or 128 bits. For example, at 10 Gbit/second the transmit traffic may be generated, by a CPU or an FPGA, 64 bits at a time at a rate of 1010/64=156.25 MHz.
To simulate single bit transmission errors it is therefore desirable to create error insertion masks of the same size and to corrupt one or more bits by bitwise XORing 64 bits of generated traffic by this error insertion mask. (XOR means exclusive OR, a logic gate that outputs true when one of two inputs to the gate is true and the other input is false.) To do this requires the generation of 64 bit (in this example) error masks at 156.25 MHz such that the total number of error bits, over time, equals the required BER.
Therefore it is desirable to provide techniques for generating such error masks, with modest hardware computing resources (FPGA logic or CPU cycles), and at a very high speed at which the network equipment testing generates the network traffic for testing.